1. Field of the Invention
The present invention is directed in general to data communications. More specifically, the present invention provides an improved method and apparatus for controlling the transfer of information between various buses in high speed data processing systems.
2. Related Art
As is known, communication technologies that link electronic devices are many and varied, servicing communications via both physical media and wirelessly. Some communication technologies interface a pair of devices, other communication technologies interface small groups of devices, and still other communication technologies interface large groups of devices.
Examples of communication technologies that couple small groups of devices include buses within digital computers, e.g., PCI (peripheral component interface) bus, ISA (industry standard architecture) bus, USB (universal serial bus), and SPI (system packet interface). One relatively new communication technology for coupling relatively small groups of devices is the HyperTransport (HT) technology, previously known as the Lightning Data Transport technology (HyperTransport I/O Link Specification “HT Standard”). The HT Standard sets forth definitions for a high-speed, low-latency protocol that can interface with today's buses like AGP, PCI, SPI, 1394, USB 2.0, and 1 Gbit Ethernet as well as next generation buses including AGP 8x, Infiniband, PCI-X, PCI 3.0, and 10 Gbit Ethernet. HT interconnects provide high-speed data links between coupled devices. Most HT enabled devices include at least a pair of HT ports so that HT enabled devices may be daisy-chained. In an HT chain or fabric, each coupled device may communicate with each other coupled device using appropriate addressing and control. Examples of devices that may be HT chained include packet data routers, server computers, data storage devices, and other computer peripheral devices, among others.
Many programming tasks, especially those that control peripheral devices require specific events to occur in a specific order. If the events generated by the program do not occur in the hardware in the order intended by the software, a peripheral device may behave in an unexpected way. Ordering or dependency rules are necessary for the correct operation of an IO bus system. However, ordering rules for one IO bus standard may not be compatible with those for another bus. Designing for a new IO bus interface for a System-On-a-Chip processor often involves re-design of the ordering rules logic section for the bus interface. There is a need, therefore, for an improved bus interface system that provides rule ordering logic that is programmable and, therefore, does not need to be redesigned when the interface is adapted to a new bus system.